发明名称 Method of regulating a digital phase-locked circuit, and a digital phase-locked circuit having a voltage-controlled oscillator
摘要 A digital phase-locked loop (1) has a counter (4) which counts pulses from a voltage controlled oscillator (8). The counter (4) is latched periodically with a period which is determined by an input signal (I) to the counter (4). The latched value is supplied to a compensation unit (5) which deducts a value which approximately corresponds to half the count counted by the counter circuit (4) when the phase lock is locked correctly. The compensated counts are supplied from the output of the compensation unit (5) to an integrator (6) and counter (9) which applies a control signal to the voltage controlled oscillator (8) via a D/A converter.
申请公布号 US6009133(A) 申请公布日期 1999.12.28
申请号 US19960755972 申请日期 1996.11.25
申请人 DSC COMMUNICATIONS A/S 发明人 NIELSEN, ANDERS B.
分类号 H03L7/085;H03L7/091;H03L7/181;(IPC1-7):H03D3/24;H03L7/00;H03L7/06 主分类号 H03L7/085
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