| 摘要 |
PCT No. PCT/JP96/02557 Sec. 371 Date May 6, 1998 Sec. 102(e) Date May 6, 1998 PCT Filed Sep. 6, 1996 PCT Pub. No. WO98/10469 PCT Pub. Date Mar. 12, 1998A transistor and a fabrication method thereof, and in particular, a technique for compatibly improving reduction of an ON-state voltage and reduction of a turn-off time. First and second emitter layers are selectively formed in isolation from each other on a surface of a base layer 3, and a channel region 6 opposed to a gate electrode 8 through a gate insulating film is formed therebetween. In an ON state, a base current Ib is supplied from a base electrode, while a prescribed gate voltage is applied to the gate electrode. The first and second emitter layers couple with each other and function as a single emitter layer, whereby the ON-state voltage becomes a low value of about the same degree as a bipolar transistor. When bringing a device into an OFF state, supply of the base current Ib is stopped while a zero (or negative) voltage is applied to the gate electrode. Consequently, coupling between the first emitter layer and the second emitter layer is canceled, whereby a second collector current Ic2 which is a component of a main current passing through the second emitter layer rapidly attenuates similarly to a MOS.
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