发明名称 MASTER SLICE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To prevent erroneous connection and to enable to perform the total connection of wires in the normal condition at a master slice semiconductor integrated circuit device by a method wherein the unnecessitated electrode pad is not provided, and moreover the total pads are provided at the positions corresponding to leads. CONSTITUTION:The leads 13 are arranged on the circumference being separated from the IC 11 in space 12 of a package accommodating the master slice IC, and terminals 15 of the same number with the electrode pads of the master slice IC having the maximum number of pins formed with the same master chip are provided on the circumferential edge of the element region covered with PSG 14. Accordingly unnecessitated terminals 152 are contained. The electrode pads 17 of the same number with the leads 13 are formed at the corresponding positions to the leads on the outside of the film 14, the pads 17 are connected to terminals 151 to be used through Al wirings 18, and are connected 19 to the corresponding leads 13. Because no unnecessitated pad exists, erroneous connection is not generated, and moreover unnatural connection is not generated, and connection can be performed properly even when a frame package of any kind is used, and productivity is enhanced.
申请公布号 JPS57190344(A) 申请公布日期 1982.11.22
申请号 JP19810075154 申请日期 1981.05.19
申请人 TOKYO SHIBAURA DENKI KK 发明人 MITANI KAZUHIRO;TOTOKI TAKASHI
分类号 H01L21/822;H01L21/60;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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