| 摘要 |
PURPOSE:To make aggregate operation efficiently in high speed, by connecting a sort engine connecting a plurality of sort processing elements in series and a merge engine connecting two merge processing elements in parallel with a common bus. CONSTITUTION:Processing is made by using two buffer memories Mk1 and Mk3 (where; k=1-n) and a memory Bk2 using FIFO function. Sort processing elements PEk consisting of a processor Pk are connected in series to constitute a sort engine SE. A merge engine ME consists of parallel connection of merge processing elements PRi comprising a buffer memory MOi (where; i=1, 2), a processor POi merge-processing through the use of memory BOi having FIFO function and an output buffer OBi. The SE and ME and connected with a common bus, the sort processing is continuously made with the control of a control processor CP, the result is inputted to the ME, RP1 and RP2 are alternately operated, data of a continuous set are sequentially merge-processed and outputted from OB1 and OB2, and the aggregate operation of data can efficiently be executed in high speed. |
