| 摘要 |
PURPOSE:To improve the processing capability through the addition of sub- units in different speed, by making report in matching with an instruction completion signal of the sub-unit having the slowest processing speed, in a device processing the result of instruction from the sub-units. CONSTITUTION:An instruction 25 from a main control unit 1 is decoded, a register 9 is selectively outputted at an interface control work fetching register readout control circuit 10 and signals 18-20 are formed. Simultaneously, instruction completion signals 21-23 are formed, they are ANDed at an AND circuit 11 to be an instruction completion signal 24 and applied to a main control unit 1. When the main control unit 1 receives the signal 24, the unit 1 fetches the outputs 18-20 from sub-units 5-7. Thus, the time between the instruction completion signal 24 is outputted and the issue of instruction is dependent on the slowest processing speed signal. |
