| 摘要 |
PURPOSE:To integrate a bipolar logic circuit and an FET into one chip by a device wherein both the high-voltage-resistance, high-speed bipolar logic circuit and the low-speed, low-power FET which is irrespective of a depth of an epitaxial layer are formed together in the common epitaxial layer separated into respective element regions with the isoplanar structure. CONSTITUTION:A low-density N<-> type epitaxial layer 2 is developed on a P type substrate 1 in a small depth of 2mum and then it is separated into respective element regions using the isoplanar technology. A bipolar Tr section comprises a high-density N<+> type collector electrode taking-out part 8 which is adjacent a buried layer 4, a P type base region 9 which is formed in the epitaxial layer 2 through diffusion, and an N<+> type emitter region 10. Since the epitaxial layer 2 has low density and is thin, the section serves as a high-voltage-resistance, high-speed logic circuit. A CMOS section includes sorce and drain regions 14, 15 in the epitaxial layer 2 and a gate electrode 17 above a gate oxide film 16, thus forming a P-MOSFET. This serves as a logic circuit of low-speed and low-consumption. |
