发明名称 MASTER SLICED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To decrease load capacitance, to improve the characteristics of the device and to ameliorate the degree of integration by directly connecting each wiring layer to the source, drain and gate regions of an MOS type transistor. CONSTITUTION:A field oxide film 12 is formed onto a semiconductor substrate 11, and the MOS type transistor consisting of the source and the drain 20, a gate oxide film and a polysilicon gate is shaped onto an element forming region. Polysilicon having high impurity concentration is formed to the extracting sections of the source and the drain 20 in the same manner as the gate section, and platinum silicide layers 22 are shaped to the surfaces. Sections among these layers are buried by oxide films 21, and flattened. The first layer metallic film 23 is molded, an insulating film 24 is grown, a desired contact hole 25 is formed, and the second layer metallic film 26 is directly connected to the silicide layer 22 without through the first layer metallic film. Accordingly, the metallic films of each layer mutually become independent, and can be contacted from the same surface.
申请公布号 JPS57188845(A) 申请公布日期 1982.11.19
申请号 JP19810074402 申请日期 1981.05.18
申请人 NIPPON DENKI KK 发明人 MATSUKUMA MOICHI
分类号 H01L29/78;H01L21/28;H01L21/82;H01L21/8234;H01L27/118;H01L29/43 主分类号 H01L29/78
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