| 摘要 |
PURPOSE:To cope with an input signal with a failure information(AIS) signal detector independently of multiplexity of the input signal, by introducing a multiplex processing technology. CONSTITUTION:In a time slot B, an RAM 6 outputs the content (a) of an address 1 to DO1-DO4 as a signal 35. Since a signal 35 given to a terminal 8 is at H level, the output signal is inputted to terminals A-D of a counter circuit 7(AIS signal detection circuit) and (a) is outputted to terminals QA-QD as an output 39 of the counter circuit 7 with the 1st clock pulse. Further, since an input signal D1-2 is at H level, the value at the terminals QA-QD is counted by one with the 2nd clock pulse in the time slot B to the a+1 and stored in the address 1 newly. On the other hand, when an input signal 31 is at H level for 15 consecutive times, an H helvel is outputted to a CARRY terminal of the counter circuit 7 and it is held at ''15'' with a NAND gate 10 and an AND gate 2 and the AIS signal is outputted at a time slot D. |
