| 摘要 |
PURPOSE:To prevent both collector currents from flowing at the same time and to eliminate current loss by a method wherein mating base voltage is cancelled by reverse base current and the rise of the mating base voltage is prevented during storage time. CONSTITUTION:Each base of switching power transistors Q1, Q2 connected in push pull fashion is closely connected by the phase suitable for push pull and each base is connected to a square wave output circuit OSC supplying square waves to each base through a risistor R4. In this way, when rising a base voltage, the square wave input is canecelled by the reverse base current during the storage time and the base voltage is risen after the storage time of the mating transistor has approached the end as shown in Drawing G. In the same way, the base current is risen with a delay as shown in Drawing H. The collector current also starts to flow with a delay as shown in Drawing I and both collector currents will not simultaneously flow during the storage time. |
