| 摘要 |
<p>PURPOSE:To quickly secure frame synchronization even in case of a circuit of an inferior quality, by resetting a frame counter in the event of continuous dissidence of a frane pattern detecting output of an output of the frame counter. CONSTITUTION:When a detecting pulse is generated from a frame pattern detecting circuit 1 for the first time, an FF 9 of a waiting circuit 7 is set, and also a detecting pulse input gate of the FF 9 is stopped. This detecting pulse sets an FF 8, too, and releases a clock input of a frame counter 6. A frame pulse outputted from a terminal Cp of the counter 6 resets the counter 6 itself, and also its time position with the detecting pulse from the circuit 1 is compared by a gate 13. Subsequently, when a dissidence pulse of both the pulses has been generated by the number N set by a counter 12, the counter 12 generates a pulse. This pulse resets the counter 6 forcibly, and also stops an input of the counter 6. Also, it resets the FF 9, and releases the detecting pulse input gate of the FF 9.</p> |
