| 摘要 |
<p>A data sequence of 1/T bits per second is encoded with min. and max. inter discontinuity intervals of T and 3T, no DC component, and a max. cumulative integral of 1.5T seconds multiplied by half the discontinuity amplitude. Data from a source synchronised by a two-phase clock are encoded by a combination of JK flip-flops and NAND gates for transmission to a discontinuity detector and decoder with a double-frequency clock. After sequence of binary 1s, an indicator signals whether or not this would introduce a DC component in normal transmission. The reconstituted NRZ-L signal is applied to a utilisation circuit. Also provided is an encoder and decoder, and for a corresp. method of code transmission with self-synchronisation.</p> |
