| 摘要 |
PURPOSE:To eliminate the special control to shorten the data for a control part and at the same time to realize a prallel process of a read data, by transferring the data read out of a reading part en bloc with each reading line and at a high speed. CONSTITUTION:When the data equivalent to a reading line is read out, the end signal is delivered to a control part 1 from a reading circuit 5. Thus the part 1 delivers the read address and the read pulse via an address bus 18. These address and pulses are fed to a memory 13 through an address switching circuit 15. Thus the contents of the memory 13 can be read through a data switching circuit 14. This read data receives the band compression at the part 1 to be fed to a circuit via a modulating part 2 and a network control part 3. Then a read start command is delivered through the part 1, an address designating counter 17 counts up to switch the address of the memory 13. Then the read data of the following line is writen into the memory 13 to be read out to the part 1. In such way, the memory 13 works alternately with each reading line. |
