| 摘要 |
PURPOSE:To realize the demultiplexing and an alteration of the buffering quantity with just a single hardware, by preventing the connection of JK-type FFs in circular tandem connection in accordance with the external signal and at the same time selecting freely the number of output stages. CONSTITUTION:D-type FF4c, 4d... are in circular tandem connection via tristate gates and AND gates 12c, 12d... and 17c, 17d.... The connection is prevented for the FF4c, 4d... according to the mode signal which is applied to the 1st decoder 9. Thus the input is interrupted for the output of the FF4e, etc. To the FF4d, etc., and the input point of the FF4d is always set at logic 1. Then the Q terminal output is inverted for each clock to be turned into an LSB of an address bit. In the same way, the Q terminal output of the FF4e, etc. is turned into an MSB, and an interleave access is given to a matrix array memory to ensure the demultiplexing with just a single hardware. In the same way, the outputs of gates 7c, 7d... are selected by a selector circuit 13 which works in response to the external signal. And the bit length is controlled to give a desired alteration to the buffering degree. |
