MULTIPLE-DRAIN MOS TRANSISTOR LOGIC GATES

摘要

1. Logic gate constituted by an inverter multidrain transistor (102 ) having an integrated monochannel enhancement mode MOS structure and by a load element (20; 30) having a contact region connected to the gate region (ZG10 ) of the inverter transistor, said gate including a first implantation plane on the surface of a semiconductor substrate of a predetermined conductivity type (1) in which are implanted the single source region (ZS10 ) and each drain region (ZD11 -ZD13 ) of the inverter transistor which are of the opposite conductivity type and are separated by the single channel region (C10 ) of the inverter transistor (102 ), and a second implantation plane constituting at least the gate region (ZG10 ) of the inverter transistor (102 ) that is composed of polycrystalline silicon (5), that is superimposed over said channel region (C10 ) through an insulating layer (3) above the first implantation plane and that is entirely surrounded by the source region (ZS10 ), characterized in that at least a drain region (ZD11 ) is separated from a neighbouring drain region (ZD12 ) through an insulating zone (ZI11-12 ) stretching from the first implantation plane to at least beyond the second implantation plane.