Integrated MOS column decoder

摘要

The invention relates to an integrated MOS column decoder having a reduced power loss and reduced layout area. The invention comprises a zero-load transistor (T7), which is series-connected to the load section and the gate of which is connected to the negated address line, which is assigned to the first switching transistor (T0) of the NOR circuit (1). Furthermore, there is a controllable voltage divider (4) between the bootstrap capacitance (CBOOT) and the parasitic barrier layer substrate capacitance (CPN). As a result, the bootstrap capacitance can be kept small enough for it to be formed only by the gate source capacitance of the zero-load transistor (T11). As a result, the layout area for the bootstrap capacitance (CBOOT) is saved and the switching speed is increased, as a result of which the switching speed of the switching transistor (T8) of the negator (2) can also be increased. The invention is used in high-speed static MOS memory circuits. <IMAGE>