| 摘要 |
PURPOSE:To reduce the electrode resistance making the pickling applicable by a method wherein the electrode wiring comprising the double conductive layers is formed by means of laminating and coating the compound conductive layer comprising a high melting point metal and silicon with the silicon layer. CONSTITUTION:The field oxide film 2 is formed in the FET region on the semiconductor substrate 1 and the gate oxide film 3 is further formed. Said oxide film 3 is continuously coated with the MOS film 4 and the poly Si film 5 as a protective layer. Then the gate electrode 6 is formed into the specified shape by means of etching the double layered material comprising said films 4 and 5. Next, the source, drain electrode 7, 8 and 12, 13 are formed to complete the single gate type MOSFET. Through these procedures, the electrode resistance may be reduced making the pickling applicable by means of providing the protective layer. |
