发明名称 SYNCHRONIZATION INSPECTING CIRCUIT FOR RECEIVER
摘要 <p>When frequency division is used as part of the clock signal regeneration process from a received data signal, a phase ambiguity may occur. A data signal receiver for a bi-phase modulated signal comprises a filter 1 feeding a sampling switch 2 which feeds a polarity detector 3 from which the decoded data is reproduced. The phase of the sampling switch 2 is controlled by the output 6-Q of a DIVIDED 2 frequency divider 6 which is driven by a phase-locked loop 5 which in turn is driven by a zero-crossing detector 4 at twice the bit frequency. A monitoring arrangement 8 has sampling switches 10 and 11 driven by outputs 6Q and 6-Q of the frequency divider 6. The data signal applied through a full-wave rectifier 9, is sampled at instants to and t1, at twice the bit frequency. The outputs of the sample switches 10 and 11 are fed to minimum voltage detectors 12 and 13, respectively, which detect the minimum value of the samples over a number of cycles of the respective input and apply this value to the inputs of a comparator 14. If the output of detector 12 is more positive than that of detector 13, the receiver is correctly synchronized but if the output of detector 13 becomes more positive than that of the detector 12, the output of the comparator changes state and causes a pulse to be applied to input 6-1 of the divider to change the phase of the divider output 6-Q.</p>
申请公布号 JPS57183149(A) 申请公布日期 1982.11.11
申请号 JP19820070170 申请日期 1982.04.26
申请人 PHILIPS' GLOEILAMPENFABRIEKEN NV 发明人 JIYON MARUKORUMU HEIRU
分类号 H04L7/00;H04L7/027 主分类号 H04L7/00
代理机构 代理人
主权项
地址