发明名称 DATA FETCHING DEVICE
摘要 <p>PURPOSE:To reduce the number of program steps or external circuits, by providing specific counter circuit, count value transferring circuit, and D type FF to fetch data synchronously without glitch with simple circuit constitution. CONSTITUTION:A counter circuit 10 which performs counting with the first clock 1 and a count value transferring circuit including a shift register circuit 20 which converts respective bit output signals 5 of the counter circuit 10 from parallel to serial and transfers them serially with the second clock 2 having a speed higher than that of the first clock 1 are provided. Further, a D type flip-flop circuit 40 is provided with uses the second clock 2 as the clock input and receives the first clock 1 in the D input terminal to supply it as the Q output to the clock input terminal of the counter circuit 10.</p>
申请公布号 JPS57182821(A) 申请公布日期 1982.11.10
申请号 JP19810069502 申请日期 1981.05.08
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SENOO TAKANORI
分类号 G06F13/42;G06F1/04;G06F15/78 主分类号 G06F13/42
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