发明名称 |
Double-data rate phase-locked-loop with phase aligners to reduce clock skew |
摘要 |
A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew. |
申请公布号 |
US6859109(B1) |
申请公布日期 |
2005.02.22 |
申请号 |
US20030250000 |
申请日期 |
2003.05.27 |
申请人 |
PERICOM SEMICONDUCTOR CORP. |
发明人 |
LEUNG GERRY C. T.;LUONG HOWARD C. |
分类号 |
H03B5/12;H03L7/099;H03L7/183;(IPC1-7):H03B27/00 |
主分类号 |
H03B5/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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