| 摘要 |
PURPOSE:To make the multiplication processing possible with the double precision operation even if the number of bits of input data is larger than the number of bits of a multiplier, by providing a holding circuit which divides an input signal to upper and lower bit sequences and holds them, a signal processing circuit for the bit shift or the like, etc. CONSTITUTION:For example, in respect to 8-bit input data, upper 4 bits are inputted to an input holder 12, and lower 4 bits are inputted to a holder 13. The output of the holder 12 and the coefficient of a coefficient equipment 4 are multiplied in a multiplier 6, and the result is supplied to a holder 7. In a signal processor 14, upper bits are shifted to lower bits bit by bit, and 0 is entered to the MSB. The output of the processor 6 and the coefficient are multiplier in the multiplier 6, and the result is supplied to the holder 7. In a signal processor 15, 8-bit data of the multiplication result is first doubled. This data is shifted to the right by 4 bits for the digit alignment to the operation result of upper bits stored in the holder 7. This output and the output of the holder 7 are added in an adder 9. |
