| 摘要 |
An input bias circuit for a charge transfer device array in which the fat zero signal level is a function of device threshold voltage and other device parameters. The use of such a circuit eliminates the need to adjust or tune the reference or bias level from array to array. The circuit includes the addition of a diode connected field effect transistor and capacitor between the input device, the source of the first charge transfer device stage, and the input gating device such that the minimum discharge level is set, on the input node, a threshold voltage drop above the reference level. When device threshold voltages are higher the charge established on the input node is decreased to compensate for the decrease in charge transferred by the register stages. Matching of the sizes of the diode connected field effect transistor with the input device and the devices in each stage of the array insures accurate tracking with process variations.
|
