| 摘要 |
PURPOSE:To avoid concentration of refresh current, by refreshing each memory block in different timing with a memory block selection signal and a refresh control signal. CONSTITUTION:Refresh addresses A0'-A6' are outputted from a refresh counter RC of a CPU and a refresh control signal Ref clock corresponding to the period of a specified address number is generated. An output of a D type flip-flop DFF applied with this clock Ref is counted with a 1/4 frequency-division counter CNT1 in response to the number of 4 memory blocks MB0-MB3 and this is processed at a decoding circuit DEC processing the clock into 4-phase. The blocks MB0-MB3 are accessed with the addresses of the same number in the timing sequentially through the logical product between the timing clock being sequentially at high level from the circuit DEC and the clock Ref for refreshing. Thus, the concentration of current can be avoided and sure refreshment can be made without using a capacitor. |
