| 摘要 |
PURPOSE:To reduce the used number of line memories by using three line memories successively for decoding, referring, and display by switching. CONSTITUTION:Gates SWD3, SWR3, and SWP3 are switched successively to use lines memories LM0, LM1, and LM2 for display, referring, and decoding successively by switching. When the memories LM0, LM1, and LM2 are used for display, referring, and decoding and the decoding of the memory LM2 ends normally, a next line is processed by using the memories LM0, LM1, and LM2 for decoding, display, and referring. When the decoding of the memory LM0 ends normally, a further succeeding line is processed by using the memories LM0, LM1, and LM2 for referring, decoding and display. If an error in transmission is detected during the decoding operation, the assignment of the line memories for display, referring, and decoding is unchanged and the processing of a next line is started. |
