| 摘要 |
PURPOSE:To incorporate a plurality of circuit elements, e.g. NAND, NOR logical functions in a single cell for integration, by dividing a junction type FET gate into two to vary the difference between gate electrodes and gate bias conditions for the combination. CONSTITUTION:A gate 6 and gate 7 provided within a substrate 9 are divided into two with each gate independently for control. When only one side impression of gate bias in inverse direction, the interval between S, D is a depletion layer not completely cut off so as to be under conductive state and, when impression on both sides of gate bias, under cut-off state for an NAND logic. Besides, the combination of gate bias produces an NOR logic. Thus, a single cell can function as a plurality of circuit elements to contrive high integration, high speed logical operation and low power consumption. |
