DDR MEMORY CORE SELECTABLE BETWEEN N-BIT AND 2N-BIT PREFETCH

摘要

A DDR(Double Data Rate) memory core is provided to improve manufacturing efficiency by manufacturing DDR memories having 4-bit and 8-bit pre-fetch structures, using the same manufacturing apparatus by selecting one of n-bit and 2n-bit pre-fetches according to market needs. Plural memory blocks(31) include plural memory cells and plural bit lines, which are connected to the memory cells. Plural local buses are formed in the respective memory blocks and connected to the bit lines. Plural global buses correspond to the respective local buses. Plural clock switches(33) are switched between the local and global buses according to first and second control signals. Both ends of the control switch are connected to corresponding local and global buses, respectively. Plural local bus connecting switches(35) switch the local buses corresponding to n/2 memory blocks in a column direction, respectively, according to a local bus connecting signal.