| 摘要 |
PURPOSE:To reduce gate capacity, increase current gain, and enhance integration by a method wherein two opposing sides of a channel of either conductivity type adjoins a gate layer of a reverse conductivity type and the other two opposing sides adjoins an insulator layer. CONSTITUTION:An n<+> layer 22 serving as a lateral pnp device Q1 base and as an n channel SIT Q2 source is buried in a p type Si substrate 10. The n<-> epitaxial layer is divided by an SiO2 layer 14 for the building of an island 16. Within the island 16, a Q1 p<+> emitter 18, a Q2 p<+> gate 20 serving also as a Q1 collector, and Q2 floating gates 22 and 24 are simultaneously formed, all of them reaching the n<+> buried layer. The n<-> layer 26 is a Q1 base and n<-> layers 28 and 30 are Q2 channels. The lateral dimensions of the layers 28 and 30 are determines so that they are pinched off with the base zero at the depletion layer. The layers 28 and 30 are respectively provided with Q2 n<+> drains 32 and 34 that are covered with an SiO2 layer 36, and ohmic electrode 38-44 are installed at prescribed locations. This construction reducing implanation of undersired carriers, the effect is weakened of minority carrier accumulation and a high speed operation is ensured, with the resultant elimination of gate current directly running into the floating gates 22 and 24 improving current gain. |
