| 摘要 |
<p>PURPOSE:To speed up the response speed to a change in a logical level of a bit signal of an address code signal, by outputting a clock signal synchronized with the address code signal. CONSTITUTION:When a logical level of a bit signal of an address code signal on an address line A0 changes from ''L'' to ''H'' level, the 1st signal S11 (output of an inverter 24) changes from ''H'' to ''L'' level. But the 2nd signal S12 (output of an inverter 25) remains ''L'' level because of a delay in the inverter 25. Thus, the output of an EXCLUSIVE-OR circuit 23 is reduced to ''L'' level, resulting in that an output terminal Pr is reduced to ''H'' level. After the time is elapsed by the delay of the inverter 25, the signal S12 changes from ''L'' to ''H'' level. Thus, the node of the circuit 23 is reduced to ''H'' and the output terminal Pr returns to ''L''.</p> |
