PROGRAMMABLE MODE OF OPERATION SELECT BY RESET AND DATA PROCESSOR USING THIS SELECT

摘要

A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches (90, 92, 96) are coupled to terminals (6) normally used as an input/output port for the data processor and the latches are clocked with a signal (88) generated by a lever detector circuit (108) which senses the reset signal (98). The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode (100) from a terminal (6) of the input/output port to the reset terminal (98) of the data processor in order to program a low logic level into the corresponding mode detection latch.