发明名称 |
HALBLEITER-SPEICHEREINRICHTUNG |
摘要 |
In addition to a main memory device a spare memory device is provided. Both memory devices utilize word wires in common which are arranged to constitute matrix circuits together with groups of bit lines. When a bit error is contained in data read out from the main memory device, a correction circuit correcting the error and a register for storing the error are provided. An output of the register is used to switch a bit line from which the error has been detected to a corresponding bit line of the spare memory device. |
申请公布号 |
DE3208763(A1) |
申请公布日期 |
1982.11.04 |
申请号 |
DE19823208763 |
申请日期 |
1982.03.11 |
申请人 |
NIPPON TELEGRAPH & TELEPHONE PUBLIC CORP. |
发明人 |
YAMADA,JUNZO;MANO,TSUNEO;INOUE,JUNICHI |
分类号 |
G11C11/413;G06F11/18;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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