| 摘要 |
PURPOSE:To prevent the ratch-up for the subject semiconductor device by a method wherein a lifetime killer is diffused in the region of thyristor structure formed between the first and the second semiconductor elements which were provided on a semiconductor substrate in the isolated state with each other. CONSTITUTION:In an integrated circuit (IC), both FET's 2 and 4 of CMOS 5 are arranged in a very close positional relations which is required to accomplish high integration. As a result, a PNPN thyristor structure is formed among a P<+> type region 13, an N type substrate 6, a P type well 3, and an N<+> type region 15. Accordingly, for the circumferential circuit part along containing the CMOS section 5, a certain kind of heavy metal, Au for example, is diffused from the back side, a metal diffusion region 25 is formed, and a ratch-up phenomenon due to the PNPN thyristor can be prevented. |
