| 摘要 |
PURPOSE:To enable to control the resistance value positively utilizing the existence of the inversion layer generated by field-effect by a method wherein the resistance value of a semiconductor layer, as the load resistor of memory cell, is controlled by applying the voltage of FET diffusion region through an insulating film. CONSTITUTION:A thin gate oxide film is formed directly below load resistors R1 and R2, and a P<+> type semiconductor regions 17 and 18, which will be coupled to drain regions 3 and 4, are formed below the gate oxide film using ion-implanting technique. In other words, an insulating gate type FET structure, wherein a P<+> type region 17 of the potential same as the drain region 4 of MOS2 is used on the side of the load resistor R1 and a a polysilicon layer R1 is used as a channel, is formed. Also, in the same manner as above, the P<+> type region 18 of the same potential as the drain region 3 of MOS1 is used as a gate on the side of the load resistor R2, and an insulating gate type FET structure having a polysilicon layer R2 as a channel is formed, thereby enabling to control the resistance value of the load resistors R1 and R2 by changing the potential of the P<+> type regions 17 and 18. |
