Method and device for synchronisation of two clock signals and a signal processor

摘要

A signal converter including a device for obtaining a sync signal (BMC) from a bits-stream (EBS), a device for signal processing (DSP) connected to the device for obtaining a sync signal and clocked with the sync signal (SYNC). A filter (HWF) is used and is connected to the signal processing device (DSP) and is clocked with a clock signal (clk). A control device is used for synchronising the clock signal (clk) with the sync signal (SYNC), in which the reference input variable of the control device is pre-determined by the sync signal (SYNC), and the controlled variable of the control device is the clock signal (clk). The control device specifically comprises a clock-pulse generator (TG). A phase comparator (PV) has a first input for the clock signal (clk), a second input for the sync signal (SYNC) and a controlled difference output connected to the control difference input of the clock pulse generator (TG).