DISPOSITIF SEQUENCEUR A MEMOIRES MORTES

摘要

A master ROM (2) is loaded with a program to control a number of operational phases of the sequencer. Several slave ROM's (3) are connected to produce different sequential signals. An output register (4) for the master ROM has several outputs connected by an address bus (5) to the address inputs on the master and slave memories. The clock inputs (CK) of the output registers (4,6) are connected to a common clock generator. The sync. signal generator is connected to a bistable (9) whose output is connected to a second bistable (10). This is connected to the unused address input on the master ROM and gives the highest weighting. The unused output (12) of the master ROM output register is connected to the clock input of the bistable while the outputs of the register for the slave ROM's are connected to control the user equipments.