| 摘要 |
PURPOSE:To make the use of the same parity ROM for 8-bit and 16-bit processors possible, by providing two 8-bit parity check circuits. CONSTITUTION:Parity check circuits 6-1 and 6-2 in 8-bit are provided, and for example, in reading out data at the address 0 by a processor, 8-bit data in the address 0 of an ROM1 and a parity bit in an ROM3 are inputted to the parity check circuit 6-1, and 8-bit data in the address 0 of an ROM2 and a parity bit of an ROM3 are inputted to the parity check circuit 6-2. Thus, in case of a 16-bit processor, the combination of data + parity bit the same as 8-bit processor is inputted to the parity check circuit to achieve common use of a parity ROM. |
