| 摘要 |
PURPOSE:To eliminate such a test pattern that produces the noise owing to the conflux of pulses, by leading the rise and fall of a pulse into a simulator. CONSTITUTION:An output of 0-X-1-X-0 is supplied to the gates 20 and 24 of a logic arithmetic circuit comprising NAND gates 20-24, etc. with the 1 piece of signal supplied to the gate 21 respectively, then the output of the gate 23 is turned into 0-Y-1-Y-0 to produce an uncertain state by the mutual logic operation of X, where X is the state of rise/fall of pulse. For instance, a test pattern with which 0 is supplied to the gates 20 and 24 along with 0-X-1-0 supplied to the gate 21 respectively is formed with the priority given to the occurrence of the uncertain state. As a result, the output of the gate 23 is turned into 0-X-0-X-1 to produce no uncertain state Y. Then the rise and fall of a pulse is led into a simulator to eliminate a pattern that produces the noise due to the conflux of pulses. Thus a test pattern suited to an LSI logic circuit, etc. is obtaind. |
