| 摘要 |
An addressing circuit has a register search counter (20) connected to a first multiplexer (24) and to a second multiplexer (25), a memory (33) connected to the output of the first multiplexer for writing the type of processing of each register, a register counter (26) connected to the second multiplexer which is itself connected by its output to three address registers (28, 30, 32) in series. The output of the second register (30) is connected to the first multiplexer to write address the memory under the control of a write signal (CRW). The register search counter read addresses the memory and stops as soon as a register requiring rapid processing is detected; the second multiplexer receives a transfer signal (ST) to transmit the address applied to the output of the register search counter; the register counter (26) stops during the transfer signal. |
