发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To realize a phase locked loop circuit with stable operation and high accuracy, by changing the direction of an up/down counter according to the phase difference and controlling a voltage controlled oscillator with a D/A converting circuit. CONSTITUTION:If a phase of a reference frequnency f1 leads, e.g., than a lock objective frequency f2, when a clock level of an output from a clock generating circuit 19 is at high level and count-up is instructed on a up/down instruction signal line 18 of level inversion, the output of an AND circuit 21 is taken as ''1'' and a clock pulse is transmitted to an up/down counter 12. Thus, the output of a D/A converter 13 receiving the output of the counter 12 is incremented by one step and a large voltage value is given to a voltage controlled oscillator 14. The phase of the frequency f2 outputted from the oscillator 14 is advanced by a specified amount and this operation is repeated. The phase of the frequency f2 approaches the frequency f1 and when both of the phases are coincident, a phase comparator 10 is made stable.
申请公布号 JPS57174939(A) 申请公布日期 1982.10.27
申请号 JP19810060314 申请日期 1981.04.21
申请人 FUJITSU KK 发明人 OBARA HIDEYUKI
分类号 H03L7/093;H03L7/08 主分类号 H03L7/093
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