发明名称 INTERRUPTION PROCESSING CIRCUIT
摘要 PURPOSE:To decrease the save area of an interruption master mask, by using a stack that saves the information to be saved when an interruption is accepted plus a master mask storing means of a bit into which the contents of each master mask are written. CONSTITUTION:When an interruption is accepted, flags C, N and Z of the masks except an interruption master mask I which are previously stored in a condition code register 10 are pushed successively from the highest part of a stack area 20 of an RAM along with the information X stored in a register 40. The contents of a master mask storing latch 30 are written according to the mask I. The latch 30 is written in the form of 1 and 0 is case the mask I is 1 and 0, respectively. As a result, the interruptions are successively accepted and each information is pushed to a stack area 20 of an RAM. And 1 is continuously written into the latch 30. When 0 is written into the latch 30, the information is just hopped thereafter.
申请公布号 JPS57174743(A) 申请公布日期 1982.10.27
申请号 JP19810060110 申请日期 1981.04.21
申请人 TOKYO SHIBAURA DENKI KK 发明人 MURAO YUTAKA
分类号 G06F9/46;G06F9/42;G06F9/48 主分类号 G06F9/46
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