发明名称 CONTROL CIRCUIT FOR INTERRUPTION PRIORITY
摘要 PURPOSE:To change the setting of the number of priority levels and the allotment of levels to each interruption in an extremely simple way, by reducing the storage area of an RAM, etc. which is used as a stack area. CONSTITUTION:The occurrence of interruption requests INT0-INT15 is informed by rising the signal lines of these requests to a high level. When a masked-off interruption request is supplied to a highest rank detecting circuit 12, the circuit 12 selects the request having the highest priority among those having the permission for acceptance. On the other hand, the information of 3 bits corresponding to the priority of the highest interruption request INT'15 is delivered from the circuit 12. The priority level information given from the circuit 14 is stored in a priority level register 16 with a certain timing when the interruption is accepted.
申请公布号 JPS57174745(A) 申请公布日期 1982.10.27
申请号 JP19810060123 申请日期 1981.04.21
申请人 TOKYO SHIBAURA DENKI KK 发明人 MURAO YUTAKA;TAKAHASHI YUKIHARU
分类号 G06F9/48 主分类号 G06F9/48
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