| 摘要 |
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single event effects. SEE-tolerant configurations (210, 210, 301, 404, 510, 520, 800) are shown and described for combinational logic circuits and state-holding logic circuits. The invention further provides SEE-tolerant configurations for SRAM memory circuits (700, 800).
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