发明名称 HIGH SPEED AND NON-VOLATILE ELECTRICALLY ERASABLE MEMORY CELL AND SYSTEM
摘要 A method is disclosed for encoding binary data into an electrically erasable memory, said memory comprising a matrix of memory cells, each of said cells comprising a floating gate field effect pMOS transistor for storage of binary data and an npn bipolar transistor for selective access to stored data. The control gate of each storage transistor in a row is connected to an X write line; the emitter of each bipolar transistor in a row is connected to an X sense line; the source of each bipolar transistor in a row is connected to a source line and the collector of each bipolar transistor in a column is connected to a Y sense line. The method comprises: (a) applying an erase voltage to each of said Y sense lines and, simultaneously, maintaining each of said X sense lines at said erase voltage, maintaining each of said X write lines at ground and applying said erase voltage to each of said source lines such that each of said storage transistors assumes a relatively negative threshold state; and (b) applying a write voltage to selected X write lines while maintaining unselected X write lines at ground, and, simultaneously, maintaining selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage which is less than said write voltage and maintaining each of said X sense lines at an intermediate voltage which is equal to or less than the base/emitter breakdown voltage of said L bipolar transistors such that the storage transistors of memory cells located at the intersections of said X write lines and said selected Y sense lines assume a relatively positive threshold state.
申请公布号 JPS57172774(A) 申请公布日期 1982.10.23
申请号 JP19810208271 申请日期 1981.12.24
申请人 FAIRCHILD CAMERA & INSTRUMENT CORP 发明人 ANDORIYUU TEIKURU;MAJIYUKAARU BII BORA
分类号 H01L27/112;G11C16/04;G11C17/00;H01L21/8246;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L27/112
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