发明名称 MULTI-PROCESSOR SYSTEM
摘要 PURPOSE:To reduce processing time in an exclusive bus system and to make both sides of software/hardware of data replacement in the common memory of bus coupling system, easy by microprogramming with a multi-operation code. CONSTITUTION:A control sustem for CPUs 1 and 2 is microprogrammed with a common operation code coupled with common buses 18 and 21, and when the common operation code is executed, a common bus control signal CRBRQ is transmitted and a series of bus control is made in response to a response input signal CRBAK. When a multi-operation code is executed, an EQ' is transmitted and when an EI is inputted, a multi-use interruption is generated, and calls such as program pointer and status and save of each register interruption are made from a specified area of an exclusive memory 8. The multi-use interruption can be masked with the software and the interruption can be ignored. When processor units 1 and 2 are in operation, the processing is made independently and in parallel to achieve the maximum processing speed.
申请公布号 JPS57172461(A) 申请公布日期 1982.10.23
申请号 JP19810058880 申请日期 1981.04.17
申请人 SHIMAZU SEISAKUSHO KK 发明人 WATANABE GENICHI
分类号 G06F15/16;G06F9/52;G06F15/167;G06F15/177 主分类号 G06F15/16
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