发明名称 DYNAMIC UNIT LOAD THEORY AND UNIT LOAD MEMORY
摘要 MOS dynamic logic/shift registers employing as load elements either a parasitic bipolar transistor whose emitter is the drain of the MOS element, or the drain-substrate diode charged via bi-polar signals on the clock lines capacitively coupled to the drain. Uses for logic, memory, and imaging applications.
申请公布号 JPS57171841(A) 申请公布日期 1982.10.22
申请号 JP19820000007 申请日期 1982.01.04
申请人 ERIYAHO HARARI 发明人 ERIYAHO HARARI
分类号 G11C19/28;H01L27/07;H01L27/105;H03K19/096 主分类号 G11C19/28
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