发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To change a response speed of a phase lock loop (PLL), by controlling a current value of a variable electric power supply by a phase lock detecting signal, in a PLL being suitable for a demodulating circuit, etc. of an AM stereophonic receiver. CONSTITUTION:A phase lock loop PLL20 is constituted of a phase comparing multiplier 21, an LPF22 for removing a carrier wave component, a band switching LPF23, a buffer circuit 24 and a voltage control oscillator VCO25. When the PLL20 enters into a lock state, a negative signal is outputted from a lock detecting circuit 17, this signal is applied to the base of a transistor TR23b, the TR23b is turned off, and a TR23j is turned off, therefore, a constant current by a constant current source 23i flows to TRs 23e, 23f. On the other hand, when the PLL20 is unlocked, a positive signal is outputted from the circuit 17, by which the TR23b is turned on, also the TR23j is turned on, and an output current of the TR23j flows to the TRs 23e, 23f. In this way, a response speed of the phase lock loop is changed under the control of the phase lock detecting signal.
申请公布号 JPS57171845(A) 申请公布日期 1982.10.22
申请号 JP19810056796 申请日期 1981.04.15
申请人 SONY KK 发明人 YOKOYA SATOSHI
分类号 H03D1/22;H03H11/04;H03K19/08;H03L7/10;H03L7/107;H04B1/26;H04H40/36 主分类号 H03D1/22
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