发明名称 PHASE LOCKED LOOP
摘要 A phase-locked loop circuit comprises an oscillator, a phase comparator which compares the phase of an input signal with the phase of an oscillator signal, a detector which detects when the phase-locked loop circuit is locked within a predetermined frequency range and produces a corresponding lock detecting signal, and a filter circuit including a variable current source which produces a variable current in response to a change of state of the lock detecting signal to control the bandwidth of the filter circuit, a filter element which receives the variable current, a differential amplifier which receives the phase-compared signal, a current mirror circuit which receives the variable current from the variable current source, and a buffer circuit connected to the filter element which supplies an output signal to the oscillator to lock the frequency of the oscillator signal to the frequency of the input signal.
申请公布号 AU8258082(A) 申请公布日期 1982.10.21
申请号 AU19820082580 申请日期 1982.04.14
申请人 SONY CORP. 发明人 NAME NOT GIVEN
分类号 H03D1/22;H03H11/04;H03K19/08;H03L7/10;H03L7/107;H04B1/26;H04H40/36 主分类号 H03D1/22
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