| 摘要 |
PURPOSE:To obtain an output with a sufficient high level at a high speed, by varying the level of the gate terminal of a transistor (TR) which connects a capacitor logical circuit part and a buffer a buffer part together. CONSTITUTION:When a timing signal P1 has a high level and the level of a point (a) is raised, the level of the point (f) of the gate terminals of TRS Q5 and Q8 rises according to the level of the point (a), assisting precharging at points b1 and b2. Further, when a precharging period ends and a decoder is to be selected, the levels of decoders drop to a low level at the point except one decoder. At this time, the point (f) is connected to all the decoder circuits in common, so the level of the point (f) falls by the point (a) of the other unselected decoder circuits. In this case, although the point (a) of the selected decoder is held at the high level, the level of the point (f) is low, so the gate TRQ5 of the selected decoder circuit turns off. Then, when a timing signal phi2 goes up to the high level, the charge of a capacitor C1 rises the level of the gate b1 of a TRQ6 and is never led to other parts. |
