| 摘要 |
PURPOSE:To obtain an instruction execution system free of latency time by calculating a desired address from the contents of a noninterfering register, the data of an instruction, and contents to be stored in an interfering register when register interference is caused. CONSTITUTION:If a B register 3' causes interference, a comparator 9' outputs a coincidence signal to close a control gate 4', and consequently an EAG5 adds the contents of an X register 3 to a data part. After the arithmetic result of a leading instruction is outputted to a result register RR13, the output of the EAG5 and the contents of the RR13 are inputted to an arithmetic circuit 12, which adds the both to calculate a logical address. In this case, a control gate 11 is opened. In case of interference of the X register, similar processing is carried out. When both the X and B registers cause interference, the result of the leading instruction is outputted to the RR13 and then multiplied by two, and the multiplication result is inputted to the arithmetic circuit, where it is added to the data part. |
