| 摘要 |
PURPOSE:To immediately obtain a sum value with a simple constitution and to achieve high-speed processing of serial data by increasing or decreasing the number of stages of shift registers according to the number of data to be added. CONSTITUTION:A shift register SR holds data up to data Dn-m which is a prescribed number of times of minus one before current data Dn, and a register REG holds a last sum value fD(n-1). A subtracter SUB finds an fD(n-1)-Dn-m, which is added to the current data Dn by an adder AD, whose sum output is supplied to the register G and held as a last sum value fD(n-1) for next arithmetic while the output of the adder AD is sent out as a current sum value fDn. A switch SW is for setting the initial value of the register REG. |
