发明名称 DIGITAL LOGIC CIRCUIT
摘要 PURPOSE:To avoid the breakdown of a digital logic circuit although a short circuit is mistakenly caused between an output terminal and a GND or between the output terminals, by providing a protecting circuit in which the output is set at L only in case the output terminal is forcibly set at L from the outside when the output terminal is set at H. CONSTITUTION:An output 3 is set at H and L when an input 1 is at L and H, respectively. Thus in this case, two inputs of a comparator 40 are not set at L simultaneously. At the same time, an output 41 is set at H to give no effect to the ordinary logic working. In case a terminal 3 is short-circuited to a GND while an input signal of H is applied to the input 1, an ON buffer output circuit 20 is cut off. Accordingly, no overcurrent flows through the circuit 20. On the other hand, if the terminal 3 is short-circuited to the GND while the input signal of L is applied to the input 1, the terminal 3 is forcibly set at L. As a result, the two inputs of the comparator 40 are set at L with the output 41 set at L. Thus the circuit 20 is cut off to break the overcurrent which is about to flow for the time of 10-20ns.
申请公布号 JPS57168527(A) 申请公布日期 1982.10.16
申请号 JP19810054012 申请日期 1981.04.10
申请人 NIPPON DENKI KK;NIHON DENKI AISHII MAIKON SYSTEM KK 发明人 MORI SUSUMU;NAKAMURA TATSUO
分类号 H03K19/088;H03K19/003 主分类号 H03K19/088
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