| 摘要 |
PURPOSE:To assuredly detect an error correction within a block, by detecting an error for each block by a cyclic redundancy check code after carrying out the error correction and detection of a subblock based on the detection bit. CONSTITUTION:A data bit of 14-bit length at right and left channels, the transmitting data of 30-bit length consisting of the cyclic redundancy check code CRCC of 2-bit length plus an inspection bit of 7-bit length are supplied to a decoding circuit 3 of 1-bit code error correction and 2-bit code error detection SEC.DED code. In case some subblock comprising the SEC.DED has the error correction detection along with an error detection for each block of CRCC, the interpolation is done for the subblock. In case on subblock has an error correction detection by the SEC.DED and an error detection exists in each block, the interpolation is given to the entire block. |
